Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO2–HfO2 (7.5 nm)–Ag/Au nc/C60 embedded HfO2 (6 nm)–HfO2 (30 nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.


Introduction
The application of nanocrystals embedded in the gate dielectrics of MOS memory devices, to improve the performance has been a topic of continued interest [1][2][3][4]. The embedding of various semiconducting (like Si, Ge) and metallic (like Ni, Ag, W, Au) nanocrystals in the gate dielectrics of MOS NVMs have been studied in this regard [2,3]. The physically separated nanoparticles/nanocrystals (ncs) present within the host dielectric, act as a charge trap sites, effectively working as a floating gate, in such devices. These nc embedded oxides have shown superior performance, in terms of better programming-erase performance, higher Fowler-Nordheim (F-N) currents, lesser write voltages and longer charge retention compared to conventional MOS memories [1][2][3][4][5][6].
From the various experimental studies, it has been firmly established that metallic nanoparticles offer more advantages than semiconducting ones, for this sort of devices. In recent studies Ag and Au ncs have shown good performance and reliability as embedded nanoparticles in MOS NVMs. With the emergence of carbon based nanomaterial like fullerenes (C60), CNTs, Carbon nanofibres etc. as potential electronic materials, study is needed on the applicability of such ncs in the gate dielectrics of MOS NVMs. Though there have been reports on CNT embedded gate oxide MOS memories [7], the use of such high aspect ratio cylindrical/wire shaped nanomaterials poses a serious challenge from the fabrication and the reliability perspective. One of the most difficult aspect of using CNTs or nanowires in gate dielectric of MOS NVMs is to prevent them from touching each other, which is essential for minimizing the charge leakage via lateral diffusion. Among the carbon based nanomaterial, C60 can be a fit candidate for embedding in gate oxide stacks of memory devices. This is due to its spherical size and smaller diameter, high work function and possible compatibility with ion-implantation process for embedding in the gate dielectric. Therefore it can be of significant interest to study and compare the performance of a C60 embedded gate oxide MOSFET memory device, with their metallic nc (Ag and Au) embedded counterparts.
Also a number of experimental and theoretical studies in recent years have shown interest in the use of compound semiconductors like InGaAs, GaN, InP etc. as substrate materials to potentially replace the Silicon substrate in certain MOSFET applications [8][9][10][11]. The compound semiconductors show certain advantages over Si MOSFETs owing to their higher electron mobility, higher density of states in the conduction band, possibility of band-gap engineering etc. However, the memory performance of such compound semiconductor MOSFETs, are a rather less explored area. Only very few reports are available to date on the application of compound semiconductors for memory applications [12][13][14][15]. In fact there has been little/no work done in the area of comparative performance of compound semiconductor MOSFET NVMs having C60 embedded gate dielectric. Therefore computational studies on the application of nanocrystal embedded gate dielectric compound semiconductor NVM devices, could act as a pointer for further experimental studies in this area.
In this work we study and compare the performance of nc-Ag/Au/C60 embedded multilayer gate dielectric long channel planar MOSFET NVM devices, using Si/GaN /InP/InGaAs as the substrate materials. The MOSFET NVM has been considered to have a multilayer gate dielectric with a stacked 5 nm SiO 2 -2.5 nm HfO 2 tunnel oxide (7.5 nm), 6 nm nc-Ag/Au/C60 embedded HfO 2 layer, followed by a 30 nm HfO 2 layer working as a control oxide. The device dimensions for our studies have been chosen so as to in the same range with recently fabricated advanced MOS-FET memories [5,6]. In our work we evaluated the MOS-FET surface potentials, the energy band diagram of the NVM, the electron tunneling characteristics (and from this the write/programming voltage), and the transient threshold voltage shifts of the device under consideration. We also modeled how the applied gate voltage impacts the threshold voltage shift due to nanocrystal charging, and investigated the erasing characteristics under a suitable reverse gate bias.

Analytical modeling
In Fig. 1 we have shown the schematic diagram (not to scale) of the device under consideration. We consider a long channel MOSFET, having n+ source and drain. The channel thickness was considered to be 20 nm (d Si ) and the channel length (L) was 100 nm. The positions of the SiO 2 tunnel oxide (d 1 ), HfO 2 tunnel oxide (d 2 ), nc embedded nitride (d 3 ) and the SiO 2 control oxide (d 4 ) were considered to be 25 nm, 27.5 nm, 33.5 nm, and 63.5 nm respectively. Which gives the thicknesses of the consecutive layers to be 5 nm (t 1 ), 2.5 nm (t 2 ), 6 nm (t 3 ) and 30 nm (t 4 ) respectively. The nanocrystals of 5 nm diameter were assumed to lie uniformly distributed within the 6 nm nc embedded HfO 2 layer. On top of it we considered an Aluminum metal gate. The device dimensions used in this paper have been chosen so as to be in the same range as with recently fabricated MOSFET memories [5,6].

Surface potential evaluation
We now move towards finding out the surface potential in the Si substrate which would act as the starting point. For y < d Si , considering only the mobile charge carriers in the Silicon the Quasi-1D Poisson's equation is given by [16][17][18] where ϕ 0 (y) stands for the potential in the Si substrate, n i is the intrinsic carrier concentration in the channel, V = 0 at the source end (x = 0) and V = V DS at the drain (x = L) and Si being the dielectric constant of the Si substrate. The other symbols having their usual meanings in the above equation. The boundary conditions for the above equation are given by In (2)-(3) the term ϕ S represents the surface potential, V G is the applied gate voltage, qΛ C (τ ) stands for the areal charge density (Coul/m 2 ) accumulated in the nc embedded layer in time τ , Φ ms stands for the gate metal-oxide work function difference. The capacitance C eff , denotes the effective capacitance of the multilayer gate oxide stack. To compute C eff , we apply the Maxwell-Garnett effective medium approximation to evaluate the effective dielectric constant of the gate oxide stack. Considering the nanocrystals to be spherical in shape and to be uniformly dispersed within the HfO 2 layer, the effective dielectric constant of embedded layer comes out to be [19] where v stands for volume fraction of nanocrystal in the nitride layer, nc stands for the nanocrystal dielectric constant of nc Si or nc Au. Here, Hf O 2 stands for the nitride dielectric constant. From this we have the capacitance of the nc embedded layer as Thereafter considering the capacitances of the different layers of dielectrics, we calculate the effective gate dielectric capacitance as In (7) C tox1 , C tox2 and C cox stand for the capacitances of the tunnel oxide (SiO 2 layer), tunnel oxide (HfO 2 layer) and the control oxide layers respectively. In order to evaluate the electron effective mass in the composite gate dielectric, we may consider the electron effective mass of the nc-Ag/Au or C60 embedded layer to be, m NC is the electron effective mass in the nc-Ag/nc-Au/C60, whereas m Hf O 2 is the electron effective mass in the HfO 2 . Thereafter, considering a single electron relaxation time throughout the entire gate dielectric, we get the effective mass of the composite gate dielectric [19], We now proceed to solve (1) using the boundary conditions (2)-(4). Initially considering the nanocrystal embedded layer to contain a constant charge N c = N C (τ 0 ) at a certain instant of time τ 0 , and following Langevelde [17], and Chen [18] we arrive at the implicit relation where υ t = (k B T /q) is the thermal potential, and ϕ F is the bulk Fermi potential, and γ is the body factor, defined by γ = 2q eff N A /C eff . Thereafter, we arrive at the expression for the surface potential where φ stands for

Field in the multilayer gate dielectric
We now turn our focus on evaluating the potential at different layers of the gate stack. For this, we consider the Poisson equations in the different layers, Here, ϕ 1 (y), ϕ 2 (y), ϕ 3 (y) and ϕ 4 (y) represent the potentials in the tunnel oxide (two layers), nc embedded nitride layer and the control oxide regions, respectively. The solutions of (15) to (17) are obtained to be respectively . . , A 8 are constants which can be determined by applying Gauss' Law at the interfaces of the layers. The values are evaluated to be Thus, the fields F 1 (x), F 2 (x) and F 3 (x) in the different regions of the gate dielectric can be found from (18)- (20) to be

Evaluation of tunneling currents and nanocrystal charging
To get the tunneling currents responsible for nanocrystal charging, we first assume a neutral nc embedded layer and solve for the surface potential as described in Sect. 2.1. Thereafter we go on to evaluate the electric fields in the different regions of the gate dielectric stack, as described in Sect. 2.2. In such devices, there exist two types of electron tunneling, the direct tunneling (occurring at low applied electric fields) and the Fowler-Nordheim (F-N) tunneling (for high applied fields). It is the F-N tunneling mechanism that is chiefly responsible for nanocrystal charging in these type of NVM. For evaluating the direct tunneling and the F-N tunneling currents, we employ a WKB approximation based model to our system [19,20]. Upon the application of a gate bias, a triangular potential well is created in the substrate side of the semiconductor-oxide interface. The quantized energy levels of this triangular potential well may be found using Here E n, is the energy of the electron in the -th valley of the n-th level (n = 1, 2, 3, . . .), q is the electronic charge, F Sub is the electric field in the substrate, m X− is the effective mass of the electron in the -th valley in the direction perpendicular to the Si-SiO 2 interface. Assuming the embedded nanocrystals and C60 to be roughly spherical in shape, their energy states are can be obtained by solving for the wave vector values of the spherical Bessel function [21] In the above expression ε i,j , is the k-th sub-band of the i-th energy state of the nanocrystal, ε g is the energy band gap, β i,k is the i-th zero of the k-th order spherical Bessel function, a being the nanocrystal size. In order to calculate the nanocrystal charging, we consider both the direct and the F-N components of the substrate to nc (J in ) and nc to metal gate tunneling (J out ) currents. The net charging current density (J Ch ) being the difference between them [19]. The F-N component of the current densities can be written as In (32)-(33), Φ B1 , Φ B2 are the intrinsic Si-SiO 2 electron tunneling barrier height, and the nanocrystal-control oxide interface barrier height.F 1 andF 3 are the equivalent fields in the region d Si < y < d 1 and d 3 < r < d 4 , respectively. The density of final states in the spherical nc is expressed as [21], ε F being the Fermi energy of the nc, (n and are free indices), other symbols have their usual meanings. The direct tunneling current components are given by The current densities J in and J out can thus be expressed as the sums of their direct and F-N components respectively. From these, the time evolution of charge stored in the nanocrystal layer, can be evaluated to be From (37), we can easily get the amount of charge stored in the nanocrystal embedded layer, which gives the stored charge density in the nanocrystal embedded layer as Equations (32)-(38) give us the write mechanism of the MOSFET device. The erase characteristics can be similarly described by considering electron tunneling from the nc states back into the Si substrate, under a negative gate bias. The erase mechanism under a negative bias is owing to the tunneling current density Φ B is the nanocrystal-tunnel oxide barrier height,F 1rev is the reverse effective (erasing) electric field density. The density of states in the substrate being where η v is the valley degeneracy, m * d is the state density effective mass m * d = (m z m y ) 1/2 where m z and m y are effective masses parallel to the semiconductor-oxide interface. k denote the Boltzmann constant and E F the substrate Fermi energy.
Here, it is worth mentioning that in our model the defects in the SiO 2 tunnel oxide-compound semiconductor interface have not been included. The presence of such interface states could induce effects such as a larger hysteresis behavior and interface trap generation, thereby hindering the performance of compound semiconductor NVMs. A solution may be offered by applying PECVD grown SiO 2 as observed by Cha et al. [12] or by the application of other dielectrics like LiNbO 3 or Gd 2 O 3 in combination with GaN/ AlGaN, as shown by Hao et al. [13] and Chang et al. [14] respectively.

Threshold voltage shifts
From Sect. 2.3, we have the value of stored charge density in the nc embedded layer. Now, we proceed to evaluate the threshold voltage shifts due to charging of the nanocrystals, following a simple method proposed by Amoroso et al. [22]. Here we consider that the charge is stored in the nc embedded layer only. If the stored charged densities at times τ and τ be given by Nc(τ ) and Nc(τ ), and their associated values of the constants A 3 and A 4 (23)-(24) be taken as A 3 , A 4 and A 3 , A 4 then the threshold voltage shift can be simply written as

Modeling results and discussions
In Figs. 2(a)-(b), we have shown the modeled surface potential with respect to a varying gate bias for the different MOSFET memory devices. For Fig. 2(a), we have assumed a fixed nanocrystal (nc-Ag) and varied the substrate. From the results it is seen that the GaN MOSFET device has a slightly higher surface potential compared to the other substrates. InP and InGaAs MOSFETs however seem to show a slightly lesser surface potential than the Si MOSFET NVM. This nature could be attributed to the relative permittivity of the substrates under consideration, GaN having a lesser k value of 8.90 compared to 11.9 of Si and 12.50 of InP and 13 of InGaAs. A lesser k-value results in a higher surface potential for the same applied gate bias. In Fig. 2(b), we have shown the surface potentials for the Si substrate MOSFET, with different ncs embedded in the gate dielectric. There doesn't seem to be much to choose from the different embedded ncs in this regard, as the difference in surface potential due to nc variation seems rather negligible. However, a critical look shows an ever so slightly lesser potential for the C60 embedded Si MOSFET compared to that of the nc-Au and the nc-Ag embedded ones. This may be due to the slight difference in the effective dielectric constants of the composite gate dielectrics, for the different cases. However, this effect is rather negligible, and hence we have not further shown the surface potential variations with a varying nc for all the three substrates, in our results. Figure 3 shows the energy band diagrams derived from our model with an (assumed) neutral nc embedded layer and a fixed gate bias of V G = +5 Volts with V DS = 0 V. Since the electron tunneling characteristics of the metallic ncs depend on their Fermi level, hence only the conduction band profile of all the cases has been shown in Fig. 3. From the band diagram it is clear that, the nanocrystals act as charge trapping sites in the multilayer gate dielectric. Here it is seen that C60 forms the deepest potential well for charge trapping, compared to the nc-Au and the nc-Ag. This is owing to the higher work function of C60 (∼5.65 eV) compared to that of the nc-Au (∼5.108 eV) and the nc-Ag (∼4.6 eV). The impact of the applied field in the writing process is also evident from the figures. In all three cases, the initiation of a triangular well formation in the substrate-tunnel SiO 2 in-terface can also be observed. The band-diagrams seem quite similar to each other. This is simply because of the semiconductors chosen are of electron affinity of a similar value (4.05, 4.14, 3.9 and 4.19 eV for Si, GaN, InP and InGaAs respectively). However a closer inspection shows a slight difference in the magnitude of the semiconductor-SiO 2 tunneling barriers for each of the systems. The InP substrate shows the least substrate to nc tunneling barrier of 2.95 eV, followed by the Si (∼3.15 eV), GaN (∼3.20 eV), and the InGaAs (∼3.24 eV) substrates.
In Fig. 4 we have shown the tunneling currents responsible for charging the nanocrystals (as derived from Sect. 2.3). As is evident from the curves, there exist two distinct regions in the gate voltage-charging current characteristics. It is the direct tunneling component of the charging current that is prominent in the low applied field region. Whereas in the high applied field region the Fowler-Nordheim currents seem to be the dominant component. Though nanocrystal charging can take place in both the domains, it is the F-N tunneling mechanism for nc charging that is more preferred due to shorter charging times and better charge pumping. However if the applied F-N stress is too high, there exists the reliability issue of device degradation. Usually it's the onset voltage of the F-N tunneling, which acts as the write/programming voltage in such devices. In all the three substrates, the C60 embedded MOSFET NVMs shows an earlier onset of the F-N tunneling mechanism. As for the substrate variation, in general the compound semiconductor devices show lesser F-N onset voltages, than the Si MOS-FET. Among the compound semiconductors InGaAs is the better performer. In Table 1 we have shown the write voltages, and the typical values of F-N tunneling currents and the direct tunneling currents in the MOSFET NVM devices under consideration.  From Table 1, it is quite clear that the C60 embedded InGaAs MOSFET NVM has the lowest write voltage, and the highest F-N tunneling currents (for a fixed applied voltage of +10 V). The performance of InGaAs is very closely followed by the GaN device. The superior performance of the compound semiconductors over Si substrate, in terms of lesser write voltages and higher F-N tunneling currents is despite a higher substrate to nc tunneling barrier. This is expected to have been originated from the higher Density of States (DOS) in the conduction band, and the higher elec- , that makes for a lesser nc to metal gate tunneling current (J out ), thereby resulting in better charging compared to the other embedded ncs. The same may be said for the superior charging performance of the Au ncs compared to the nc Ag embedded dielectrics.
At this point, it is worth mentioning that, is in this work we have considered metal ncs of 5 nm diameter (which is the standard average size of nanoclusters used in nc embedded gate dielectric MOS NVMs) [1][2][3][4][5][6][7][8][9]. Using a smaller sized metallic ncs (say ∼2 nm diameter) may result in improvement of the charging and the leakage suppression performance of MOS NVMs by virtue of the work-function enhancement of the ncs. Such effects have also been studied in our earlier work on Si MOSCAP NVM [23]. Since the focus of the present article is on the performance of compound semiconductor MOSFET NVMs, therefore a thorough study on the size variation of ncs on the NVM performance are beyond the scope of this work.
In MOSFET NVMs, the most important parameter is the threshold voltage shift. It is by this parameter that the 0 and 1 state of a MOSFET memory device may be understood. The higher the threshold shift for a given condition, the better is the performance of the NVM. In Fig. 5, we have shown the variations of the threshold voltage shifts, with different applied gate voltages. We have assumed a fixed charging time of 10 −2 seconds. Owing to the lesser write voltages and a higher Density of States (DOS), the C60 embedded devices seem to offer the best performance followed by nc-Au and nc-Ag embedded NVMs. For similar reasons, the compound semiconductor MOSFETs perform better than the Si MOSFETs, in terms of obtaining higher threshold voltage shifts for the same applied gate voltage. In Fig. 6, we have shown a comparison of the threshold voltage shifts evaluated from our model, with experimental results of Mikhelashvili et al. [5] for nc-Au embedded Si MOSFET NVM device reported recently. For the comparison, we have plugged into our model, the exact device dimensions as for the fabricated device [6].
In Figs. 7(a)-(d), we have shown the transient threshold voltage shifts of the various devices under consideration, for a fixed applied gate voltage of +9 Volts. As evident from the results, the compound semiconductor MOSFET memories seem to show not only higher magnitude of threshold voltage shifts, but they also seem to charge significantly faster. This is owing to the higher magnitude of F-N tunneling currents for the compound semiconductor MOSFETs, in   [5] comparison to the Si MOSFET. Also, the lower write voltage, and the slightly higher density of final states in the C60 enable them to fare better than the other ncs under consideration.
In Figs. 8(a)-(c), we have shown the comparison of results of our model for transient threshold shifts, with experimental data of recently fabricated nc-Ag embedded MOS-FET NVM by Ryu et al. [6] and that of nc-Au embedded MOSFET NVMs by Mikhelashvili et al. [5].
Here, we have considered both the electron charging and the hole charging cases of the devices under consideration, and used device dimensions identical to those reported by the aforesaid groups [5,6]. The results seem to show good agreement with the experimental data.
Finally in Figs. 9(a)-(d) we have shown the modeled erase characteristics of different nc embedded gate dielectric MOSFET NVMs, for a fixed erasing voltage of −8.5 V. All the devices were considered to initially charge at an applied gate bias of +9 V for 10 −2 s. The C60 embedded devices show to take longer time to erase, owing to their deeper potential well (which effectively suppresses nc to substrate tunneling currents), followed by the nc-Au and nc-Ag embedded devices. Among the compound semiconductor MOS-FETs, it is the InP MOS that shows slightly longer erase times compared to the GaN. From the point of view of the erase time the InGaAs MOS NVM shows the fastest erase characteristics. For the Si MOSFET, however the erase time is the more. This can be attributed to the fact that the compound semiconductor MOSFET NVM acquires more charge than the Si substrate MOSFET. This higher amount of stored  charge can act to cause a faster erase mechanism by enhancing the reverse (erasing) gate bias.

Conclusion
In this work we study and compare the performance of different nanocrystal (nc-Ag/nc-Au/C60) embedded multilayer gate dielectric long channel MOSFET NVM devices. We compared two compound semiconductors namely, GaN and InP for use as proposed substrate materials in such NVMs, with the conventional Si substrate in our study. From a semianalytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter we have investigated the Fowler Nordheim and the direct tunneling currents from the substrate inversion layer to the embedded nanocrystal states in such devices, using following a traplike model using a WKB approximation based method. We simulated the write-erase characteristics, gate tunneling currents, transient threshold voltage shifts of the NVM devices from our analytical model. The results of the simulations were also compared with recently reported experimental results for nc-Ag and nc-Au embedded MOSFET NVMs.
From the studies, the C60 embedded gate dielectric devices showed better performance than the ones embedded with nc-Ag and nc-Au, in terms of lower write/programming voltages, higher magnitude of threshold voltage shift and faster charging, for the same applied gate voltage and better charge retention properties. These results stem from the fact that C60 has a higher work-function than the metallic ncs, which forms deeper potential well in the gate dielectric, helping in better charging performance and charge storage. Among the two metallic ncs the nc-Au embedded device emerged as the better performer from our simulations. The comparison between the different substrates shows an overall superior memory performance of the compound semiconductor MOSFETs, with GaN emerging as the best choice. The results predicted by our model seems to be in good agreement with available data on metallic ncs embedded gate dielectric MOSFET memories.
From these we could propose C60 embedded GaN MOS-FET to be a better replacement of the currently used metallic nc-Ag or nc-Au embedded conventional Si MOSFET memory devices.