http://sedici.unlp.edu.ar:80/handle/10915/373 2013-05-22T18:59:11Z 2013-05-22T18:59:11Z Russo, Claudia Cecilia http://sedici.unlp.edu.ar:80/handle/10915/9413 2013-01-04T17:21:11Z 2001-01-01T00:00:00Z

Revision Journal of Computer Science & Technology; vol. 1, no. 4 Video compression is one of the topics included in the area of images digital processing. The book gives an introduction to algorithms and architectures used in standard video and audio compression

2001-01-01T00:00:00Z Video compression is one of the topics included in the area of images digital processing. The book gives an introduction to algorithms and architectures used in standard video and audio compression Villagarcía Wanza, Horacio A. http://sedici.unlp.edu.ar:80/handle/10915/9412 2013-01-04T17:22:05Z 2001-01-01T00:00:00Z

Revision Journal of Computer Science & Technology; vol. 1, no. 4 The book intends to address the important aspects of high-performance signal processing with a focus on the recent development of VLSI technology for signal processing. The editors collect much of all the research efforts and findings that have made high performance implementation of signal processing possible in the last decade in two volumes.

2001-01-01T00:00:00Z The book intends to address the important aspects of high-performance signal processing with a focus on the recent development of VLSI technology for signal processing. The editors collect much of all the research efforts and findings that have made high performance implementation of signal processing possible in the last decade in two volumes. Ruedín, Ana M. C. http://sedici.unlp.edu.ar:80/handle/10915/9411 2012-05-10T22:01:05Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 In a general context we introduce image processing with 1-dimensional wavelets and show the diferences with nonseparable 2-dimensional wavelets having quincunx decimation, in the first place, and with balanced nonseparable 2-dimensional multiwavelets, in the second place. All of them are orthogonal. Formulae for analysis and synthesis are given for the latter. The first steps are illustrated with images. The decomposition of the original image into 2 input images is explained. We illustrate with examples 2 applications: zoom-in (interpolation) and compression of images.

2001-01-01T00:00:00Z In a general context we introduce image processing with 1-dimensional wavelets and show the diferences with nonseparable 2-dimensional wavelets having quincunx decimation, in the first place, and with balanced nonseparable 2-dimensional multiwavelets, in the second place. All of them are orthogonal. Formulae for analysis and synthesis are given for the latter. The first steps are illustrated with images. The decomposition of the original image into 2 input images is explained. We illustrate with examples 2 applications: zoom-in (interpolation) and compression of images. Tinetti, Fernando Gustavo http://sedici.unlp.edu.ar:80/handle/10915/9410 2012-05-10T22:01:05Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 Parallel computing on networks of workstations are intensively used in some application areas such as linear algebra operations. Topics such as processing as well as communication hardware heterogeneity are considered solved by the use of parallel processing libraries, but experimentation about performance under these circumstances seems to be necessary. Also, installed networks of workstations are specially attractive due to its extremely low cost for parallel processing as well as its great availability given the number of installed local area networks. The performance of such networks of workstations is fully analyzed by means of a simple application: matrix multiplication. A parallel algorithm is proposed for matrix multiplication derived from two main sources: a) previous proposed algorithms for this task in traditional parallel computers, and b) the bus based interconnection network of workstations. This parallel algorithm is analyzed experimentally in terms of workstations workload and data communication, two main factors in overall parallel computing performance.

2001-01-01T00:00:00Z Parallel computing on networks of workstations are intensively used in some application areas such as linear algebra operations. Topics such as processing as well as communication hardware heterogeneity are considered solved by the use of parallel processing libraries, but experimentation about performance under these circumstances seems to be necessary. Also, installed networks of workstations are specially attractive due to its extremely low cost for parallel processing as well as its great availability given the number of installed local area networks. The performance of such networks of workstations is fully analyzed by means of a simple application: matrix multiplication. A parallel algorithm is proposed for matrix multiplication derived from two main sources: a) previous proposed algorithms for this task in traditional parallel computers, and b) the bus based interconnection network of workstations. This parallel algorithm is analyzed experimentally in terms of workstations workload and data communication, two main factors in overall parallel computing performance. Ruscuni, Sebastián Bertone, Rodolfo Alfredo http://sedici.unlp.edu.ar:80/handle/10915/9409 2012-05-10T22:01:05Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 This paper presents an evolution of a simulation environment where situations in which a DDB should maintain data integrity are modeled and implemented. These situations include failures taking place during transactions, and the focus is mainly on the utilization and later comparison of different atomic commit protocols (ACP). The implementation was made on Java due to different aspects such as ease of work, portability, etc. The environment is mainly based on failure recovery of transactions in a distributed data environment, and it allows to choose for the simulation development between two-phase, three-phase, optimistic and pessimistic protocols. The task scheduler defined and implemented to carry out each simulation, based on an execution design establishing each specific problem to be solved, is also specified.

2001-01-01T00:00:00Z This paper presents an evolution of a simulation environment where situations in which a DDB should maintain data integrity are modeled and implemented. These situations include failures taking place during transactions, and the focus is mainly on the utilization and later comparison of different atomic commit protocols (ACP). The implementation was made on Java due to different aspects such as ease of work, portability, etc. The environment is mainly based on failure recovery of transactions in a distributed data environment, and it allows to choose for the simulation development between two-phase, three-phase, optimistic and pessimistic protocols. The task scheduler defined and implemented to carry out each simulation, based on an execution design establishing each specific problem to be solved, is also specified. Lanzarini, Laura Cristina De Giusti, Armando Eduardo http://sedici.unlp.edu.ar:80/handle/10915/9408 2012-05-10T22:01:05Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 The proposal of this research line is the search for alternatives to the resolution of complex problems where human knowledge should be apprehended in a general fashion. In particular, the activities developed so far can be included in the area of Medical Diagnosis, even though similar applications in other fields are not discarded. In general, one of the greatest problems of medical diagnosis is the subjectivity of the specialist. The experience of the professional greatly affects the final diagnosis. This is due to the fact that the result does not depend on a systematized solution, but on the interpretation of the patient´s answer. The solution to this kind of problems can be found in the area of Adaptive Pattern Recognition, where the solution rests on the easiness with which the systems adapts to the information available, in this case coming from the patient. In this sense, neural networks are extremely useful, since they are not only capable of learning with the aid of an expert, but they can also make generalizations based on the information from the input data, thus showing relations that are a priori of a complex nature.

2001-01-01T00:00:00Z The proposal of this research line is the search for alternatives to the resolution of complex problems where human knowledge should be apprehended in a general fashion. In particular, the activities developed so far can be included in the area of Medical Diagnosis, even though similar applications in other fields are not discarded. In general, one of the greatest problems of medical diagnosis is the subjectivity of the specialist. The experience of the professional greatly affects the final diagnosis. This is due to the fact that the result does not depend on a systematized solution, but on the interpretation of the patient´s answer. The solution to this kind of problems can be found in the area of Adaptive Pattern Recognition, where the solution rests on the easiness with which the systems adapts to the information available, in this case coming from the patient. In this sense, neural networks are extremely useful, since they are not only capable of learning with the aid of an expert, but they can also make generalizations based on the information from the input data, thus showing relations that are a priori of a complex nature. Baum, Gabriel Alfredo Aguirre, Nazareno Matías Arroyo, Marcelo http://sedici.unlp.edu.ar:80/handle/10915/9407 2012-05-10T22:01:06Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 In this work a compiler from fork specifications into logic programs is presented. The technique implemented by the compiler consists of transforming a set of fork equations (with some restrictions) into normal logic programs in such a way that the semantics of the fork equations is preserved. After translating a fork specification, it can be executed by consulting the generated logic program. The fork compiler, a tool for the translation, is also introduced.

2001-01-01T00:00:00Z In this work a compiler from fork specifications into logic programs is presented. The technique implemented by the compiler consists of transforming a set of fork equations (with some restrictions) into normal logic programs in such a way that the semantics of the fork equations is preserved. After translating a fork specification, it can be executed by consulting the generated logic program. The fork compiler, a tool for the translation, is also introduced. Chesñevar, Carlos Iván Simari, Guillermo Ricardo http://sedici.unlp.edu.ar:80/handle/10915/9406 2012-05-10T22:01:06Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 In the last years there has been and increasing demand of a variety of logical systems, prompted mostly by applications of logic in AI, logic programming an other related areas. Labeled Deductive Systems (LDS) were developed as a flexible methodology to formalize such a kind of complex logical systems. In the last decade, defeasible argumentation has proven to be a confluence point for many approaches to formalizing commonsense reasoning. Different formalisms have been developed, many of them sharing common features. This paper presents a formalization of an LDS for defeasible argumentation, in wich the main issues concerning defeasible argumentation are captured a unified logical framework.The propose framework is defined in two stages. First, defeasible inference will be formalized by characterizing and argumentative LDS. That system will be then extended in order to capture conflict among arguments using a dialectal approach. We also present some logical properties emerging from the proposed framework, discussing also its semantical characterization.

2001-01-01T00:00:00Z In the last years there has been and increasing demand of a variety of logical systems, prompted mostly by applications of logic in AI, logic programming an other related areas. Labeled Deductive Systems (LDS) were developed as a flexible methodology to formalize such a kind of complex logical systems. In the last decade, defeasible argumentation has proven to be a confluence point for many approaches to formalizing commonsense reasoning. Different formalisms have been developed, many of them sharing common features. This paper presents a formalization of an LDS for defeasible argumentation, in wich the main issues concerning defeasible argumentation are captured a unified logical framework.The propose framework is defined in two stages. First, defeasible inference will be formalized by characterizing and argumentative LDS. That system will be then extended in order to capture conflict among arguments using a dialectal approach. We also present some logical properties emerging from the proposed framework, discussing also its semantical characterization. Belloni, Edgardo A. http://sedici.unlp.edu.ar:80/handle/10915/9405 2012-05-10T22:01:06Z 2001-01-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 1, no. 4 Mobile agent systems have received important attention in the last years as a new programming paradigm for widely distributed and heterogeneous systems. In this article, a multi-paradigm approach for the development of intelligent mobile agents is presented. It integrates both object-oriented and logic paradigms. The rationale for this approach comes from the fact that although the object-oriented programming paradigm has relevant features for mobile agent development it presents deficiencies dealing with agents mental attitudes. These deficiencies are solved by the use of logic programming.

2001-01-01T00:00:00Z Mobile agent systems have received important attention in the last years as a new programming paradigm for widely distributed and heterogeneous systems. In this article, a multi-paradigm approach for the development of intelligent mobile agents is presented. It integrates both object-oriented and logic paradigms. The rationale for this approach comes from the fact that although the object-oriented programming paradigm has relevant features for mobile agent development it presents deficiencies dealing with agents mental attitudes. These deficiencies are solved by the use of logic programming. Moure, Juan Carlos Rexachs del Rosario, Dolores Luque Fadón, Emilio http://sedici.unlp.edu.ar:80/handle/10915/9404 2012-05-10T22:01:07Z 2001-01-01T00:00:00Z

Articulo vol. 1, no. 4 Continuous IC process enhancements make possible to integrate on a single chip the re-sources required for simultaneously executing multiple control flows or threads, exploiting different levels of thread-level parallelism: application-, function-, and loop-level. Scalable simultaneous multi-threading combines static and dynamic mechanisms to assemble a complexity-effective design that provides high instruction per cycle rates without sacrificing cycle time nor single-thread performance. This paper addresses the design of the fetch unit for a high-performance, scalable, simultaneous multithreaded processor. We present the detailed microarchitecture of a clustered and reconfigurable fetch unit based on an existing single-thread fetch unit. In order to minimize the occurrence of fetch hazards, the fetch unit dynamically adapts to the available thread-level parallelism and to the fetch characteristics of the active threads, working as a single shared unit or as two separate clusters. It combines static and dynamic methods in a complexity-efficient way. The design is supported by a simulation- based analysis of different instruction cache and branch target buffer configurations on the context of a multithreaded execution workload. Average reductions on the miss rates between 30% and 60% and peak reductions greater than 200% are obtained.

2001-01-01T00:00:00Z Continuous IC process enhancements make possible to integrate on a single chip the re-sources required for simultaneously executing multiple control flows or threads, exploiting different levels of thread-level parallelism: application-, function-, and loop-level. Scalable simultaneous multi-threading combines static and dynamic mechanisms to assemble a complexity-effective design that provides high instruction per cycle rates without sacrificing cycle time nor single-thread performance. This paper addresses the design of the fetch unit for a high-performance, scalable, simultaneous multithreaded processor. We present the detailed microarchitecture of a clustered and reconfigurable fetch unit based on an existing single-thread fetch unit. In order to minimize the occurrence of fetch hazards, the fetch unit dynamically adapts to the available thread-level parallelism and to the fetch characteristics of the active threads, working as a single shared unit or as two separate clusters. It combines static and dynamic methods in a complexity-efficient way. The design is supported by a simulation- based analysis of different instruction cache and branch target buffer configurations on the context of a multithreaded execution workload. Average reductions on the miss rates between 30% and 60% and peak reductions greater than 200% are obtained.