http://sedici.unlp.edu.ar:80/handle/10915/393 2026-05-19T10:13:28Z 2026-05-19T10:13:28Z Nazrul Islam, Muhammad http://sedici.unlp.edu.ar:80/handle/10915/9642 2019-06-21T04:03:36Z 2008-10-01T00:00:00Z

Revision Journal of Computer Science & Technology; vol. 8, no. 3 The growth of technological innovations, internet developments, and their (web) applications has raised a definite issue on retaining the web interface quite understandable, and a need is also being felt on developing suitable and coherent guidelines for designing interface to swell the user interpretability of web signs. These design principles are semiotics by nature and semiotics is the science of signs, that is, of meaning’s representations. For this, new and important perspectives for interface design would be discovered by Semiotic Analysis on interface signs. Therefore, this research mainly focuses on the valuable insights that semiotic analysis could offer to present the fundamental concepts to create understandable signs.

2008-10-01T00:00:00Z The growth of technological innovations, internet developments, and their (web) applications has raised a definite issue on retaining the web interface quite understandable, and a need is also being felt on developing suitable and coherent guidelines for designing interface to swell the user interpretability of web signs. These design principles are semiotics by nature and semiotics is the science of signs, that is, of meaning’s representations. For this, new and important perspectives for interface design would be discovered by Semiotic Analysis on interface signs. Therefore, this research mainly focuses on the valuable insights that semiotic analysis could offer to present the fundamental concepts to create understandable signs. Tinetti, Fernando Gustavo http://sedici.unlp.edu.ar:80/handle/10915/9641 2019-06-21T04:03:34Z 2008-10-01T00:00:00Z

Revision Journal of Computer Science & Technology; vol. 8, no. 3 An updated edition of the classic book on computer architecture by J. L. Hennessy and D. A. Patterson. Authors show their high level standards for technological ideas, writing style, and teaching methodologies, all in one book. In fact, they maintain their quality since the first edition of this book. As authors explain, one of the main reasons for the fourth edition of the book is the focus on parallel architectures for high performance, more specifically: multiple processors or processors cores per chip designs.

2008-10-01T00:00:00Z An updated edition of the classic book on computer architecture by J. L. Hennessy and D. A. Patterson. Authors show their high level standards for technological ideas, writing style, and teaching methodologies, all in one book. In fact, they maintain their quality since the first edition of this book. As authors explain, one of the main reasons for the fourth edition of the book is the focus on parallel architectures for high performance, more specifically: multiple processors or processors cores per chip designs. Aragón, Victoria S. Esquivel, Susana Cecilia Coello Coello, Carlos http://sedici.unlp.edu.ar:80/handle/10915/9640 2019-06-21T04:03:32Z 2008-10-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 8, no. 3 In this paper, we present a new model of an artificial immune system (AIS), based on the process that suffers the T-Cell, it is called T-Cell Model. It is used for solving constrained (numerical) optimization problems. The model operates on three populations: Virgins, Effectors and Memory. Each of them has a different role. Also, the model dynamically adapts the tolerance factor in order to improve the exploration capabilities of the algorithm. We also develop a new mutation operator which incorporates knowledge of the problem. We validate our proposed approach with a set of test functions taken from the specialized literature and we compare our results with respect to Stochastic Ranking (which is an approach representative of the state-of-theart in the area), with respect to an AIS previously proposed and a self-organizing migrating genetic algorithm for constrained optimization (C-SOMGA).

2008-10-01T00:00:00Z In this paper, we present a new model of an artificial immune system (AIS), based on the process that suffers the T-Cell, it is called T-Cell Model. It is used for solving constrained (numerical) optimization problems. The model operates on three populations: Virgins, Effectors and Memory. Each of them has a different role. Also, the model dynamically adapts the tolerance factor in order to improve the exploration capabilities of the algorithm. We also develop a new mutation operator which incorporates knowledge of the problem. We validate our proposed approach with a set of test functions taken from the specialized literature and we compare our results with respect to Stochastic Ranking (which is an approach representative of the state-of-theart in the area), with respect to an AIS previously proposed and a self-organizing migrating genetic algorithm for constrained optimization (C-SOMGA). González, Mariela A. Cuadrado, Teresita R. Ballarín, Virginia Laura http://sedici.unlp.edu.ar:80/handle/10915/9639 2019-06-21T04:03:31Z 2008-10-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 8, no. 3 Segmentation is often a critical step in image analysis. Microscope image components show great variability of shapes, sizes, intensities and textures. An inaccurate segmentation conditions the ulterior quantification and parameter measurement. The Watershed Transform is able to distinguish extremely complex objects and is easily adaptable to various kinds of images. The success of the Watershed Transform depends essentially on the existence of unequivocal markers for each of the objects of interest. The standard methods of marker detection are highly specific, they have a high computational cost and they determine markers in an effective but not automatic way when processing highly textured images. This paper compares two different pattern recognition techniques proposed for the automatic detection of markers that allow the application of the Watershed Transform to biomedical images acquired via a microscope. The results allow us to conclude that the method based on clustering is an effective tool for the application of the Watershed Transform.

2008-10-01T00:00:00Z Segmentation is often a critical step in image analysis. Microscope image components show great variability of shapes, sizes, intensities and textures. An inaccurate segmentation conditions the ulterior quantification and parameter measurement. The Watershed Transform is able to distinguish extremely complex objects and is easily adaptable to various kinds of images. The success of the Watershed Transform depends essentially on the existence of unequivocal markers for each of the objects of interest. The standard methods of marker detection are highly specific, they have a high computational cost and they determine markers in an effective but not automatic way when processing highly textured images. This paper compares two different pattern recognition techniques proposed for the automatic detection of markers that allow the application of the Watershed Transform to biomedical images acquired via a microscope. The results allow us to conclude that the method based on clustering is an effective tool for the application of the Watershed Transform. Sibai, Fadi N. http://sedici.unlp.edu.ar:80/handle/10915/9638 2019-06-21T04:03:30Z 2008-10-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 8, no. 3 Asymmetric or heterogeneous multi-core (AMC) architectures have definite performance, performance per watt and fault tolerance advantages for a wide range of workloads. We propose a 16 core AMC architecture mixing simple and complex cores, and single and multiple thread cores of various power envelopes. A priority-based thread scheduling algorithm is also proposed for this AMC architecture. Fairness of this scheduling algorithm vis-a-vis lower priority thread starvation, and hardware and software requirements needed to implement this algorithm are addressed. We illustrate how this algorithm operates by a thread scheduling example. The produced schedule maximizes throughput (but is priority-based) and the core utilization given the available resources, the states and contents of the starting queues, and the threads' core requirement constraints. A simulation model simulates 6 scheduling algorithms which vary in their support of core affinity and thread migration. The simulation results that both core affinity and thread migration positively effect the completion time and that the nearest neighbor scheduling algorithm outperforms or is competitive with the other algorithms in all considered scenarios

2008-10-01T00:00:00Z Asymmetric or heterogeneous multi-core (AMC) architectures have definite performance, performance per watt and fault tolerance advantages for a wide range of workloads. We propose a 16 core AMC architecture mixing simple and complex cores, and single and multiple thread cores of various power envelopes. A priority-based thread scheduling algorithm is also proposed for this AMC architecture. Fairness of this scheduling algorithm vis-a-vis lower priority thread starvation, and hardware and software requirements needed to implement this algorithm are addressed. We illustrate how this algorithm operates by a thread scheduling example. The produced schedule maximizes throughput (but is priority-based) and the core utilization given the available resources, the states and contents of the starting queues, and the threads' core requirement constraints. A simulation model simulates 6 scheduling algorithms which vary in their support of core affinity and thread migration. The simulation results that both core affinity and thread migration positively effect the completion time and that the nearest neighbor scheduling algorithm outperforms or is competitive with the other algorithms in all considered scenarios Pessolani, Pablo Andrés http://sedici.unlp.edu.ar:80/handle/10915/9637 2019-06-21T04:03:29Z 2008-10-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 8, no. 3 MINIX4RT is an extension of the well-known MINIX Operating System that adds Hard Real-Time services in a new microkernel but keeping backward compatibility with standard MINIX versions. Semaphores are the primitive synchronization and mutual exclusion mechanism in many operating systems, but MINIX does not provide those facilities. Semaphores were added to MINIX4RT, and since it is a Real-Time Operating System, they must meet some processing requirements such as dequeueing waiting processes in priority order and avoiding the Priority Inversion problem. This article describes the Real-Time Semaphores facilities available on MINIX4RT, its design, implementation, performance tests and their results.

2008-10-01T00:00:00Z MINIX4RT is an extension of the well-known MINIX Operating System that adds Hard Real-Time services in a new microkernel but keeping backward compatibility with standard MINIX versions. Semaphores are the primitive synchronization and mutual exclusion mechanism in many operating systems, but MINIX does not provide those facilities. Semaphores were added to MINIX4RT, and since it is a Real-Time Operating System, they must meet some processing requirements such as dequeueing waiting processes in priority order and avoiding the Priority Inversion problem. This article describes the Real-Time Semaphores facilities available on MINIX4RT, its design, implementation, performance tests and their results. Castro, Fernando Chaver, Daniel Piñuel, Luis Prieto, Manuel Tirado Fernández, Francisco http://sedici.unlp.edu.ar:80/handle/10915/9636 2019-06-21T04:03:27Z 2008-10-01T00:00:00Z

Articulo Journal of Computer Science & Technology; vol. 8, no. 3 One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.

2008-10-01T00:00:00Z One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.