A system to detect timing problems in digital circuits

Abstract

Nowadays, the digital circuit production is carried out spec- ifying the circuit functionality using a hardware description language. Then, this speci cation is synthesized down to a structural netlist suit- able for use by the target technologys place-and-route applications. Many synthesis tools make this task introducing some unnecessary gates and wires in the nal circuit. As a consequence, it can appear a circuit con- taining one or more paths that do not in uence the circuit output. This kind of non-relevant paths is known as False Path. The problem with false paths is that if they are not considered, the circuit delay may be overestimated during design analysis and optimization. For this reason, the digital circuit industry is looking for e ective methods and tools to overcome the mentioned drawbacks. This paper presents a system to detect False Paths based on the analysis of the circuit intermediate speci cation. The tool analyzes the speci ca- tion using compilation techniques and then applies some special purpose algorithms for detecting false paths. Furthermore, it shows the gates and wires that are not necessary for the circuit nal version.