Upload resources

Upload your works to SEDICI to increase its visibility and improve its impact

 

Show simple item record

dc.date.accessioned 2012-08-07T16:30:50Z
dc.date.available 2012-08-07T16:30:50Z
dc.date.issued 2010
dc.identifier.uri http://hdl.handle.net/10915/19296
dc.description.abstract Nowadays, the digital circuit production is carried out specifying the circuit functionality using a hardware description language. Then, this specification is synthesized down to a structural netlist suitable for use by the target technologys place-and-route applications. Many synthesis tools make this task introducing some unnecessary gates and wires in the final circuit. As a consequence, it can appear a circuit containing one or more paths that do not influence the circuit output. This kind of non-relevant paths is known as False Path. The problem with false paths is that if they are not considered, the circuit delay may be overestimated during design analysis and optimization. For this reason, the digital circuit industry is looking for effective methods and tools to overcome the mentioned drawbacks. This paper presents a system to detect False Paths based on the analysis of the circuit intermediate specification. The tool analyzes the specification using compilation techniques and then applies some special purpose algorithms for detecting false paths. Furthermore, it shows the gates and wires that are not necessary for the circuit final version. en
dc.format.extent p. 616-625 es
dc.language es es
dc.title A system to detect timing problems in digital circuits en
dc.type Objeto de conferencia es
sedici.identifier.isbn 978-950-9474-49-9 es
sedici.creator.person Pelaez, Esteban es
sedici.creator.person Berón, Mario es
sedici.creator.person Salgado, Carlos Humberto es
sedici.creator.person Peralta, Mario es
sedici.creator.person Baigorria, Lorena es
sedici.creator.person Garis, Ana Gabriela es
sedici.creator.person Montejano, Germán Antonio es
sedici.creator.person Riesco, Daniel Eduardo es
sedici.creator.person Henriques, Pedro Rangel es
sedici.description.note Presentado en el VII Workshop Ingeniería de Software (WIS) es
sedici.subject.materias Ciencias Informáticas es
sedici.subject.keyword false path en
sedici.subject.keyword syntactic analysis en
sedici.subject.keyword semantic analysis en
sedici.subject.keyword hardware description languages en
sedici.subject.keyword intermediate language en
sedici.description.fulltext true es
mods.originInfo.place Red de Universidades con Carreras en Informática (RedUNCI) es
sedici.subtype Objeto de conferencia es
sedici.rights.license Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
sedici.rights.uri http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
sedici.date.exposure 2010-10
sedici.relation.event XVI Congreso Argentino de Ciencias de la Computación es
sedici.description.peerReview peer-review es
sedici.subject.acmcss98 SOFTWARE ENGINEERING es


Files in this item

This item appears in the following Collection(s)

Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) Except where otherwise noted, this item's license is described as Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)