Application of a Genetic Algorithm in a Fault-tolerant Filter

Abstract

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.