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dc.date.accessioned | 2023-08-18T16:35:43Z | |
dc.date.available | 2023-08-18T16:35:43Z | |
dc.date.issued | 2022 | |
dc.identifier.uri | http://sedici.unlp.edu.ar/handle/10915/156595 | |
dc.description.abstract | Objective: Fully differential topologies are wellsuited for biopotential amplifiers, mainly for single-supply battery-powered circuits such as portable wearable devices where a reduced number of parts is desired. A novel fully differential biopotential amplifier is proposed with the goal of providing electrode offset rejection, bandwidth limitation, and a temporal response compliant with biomedical standards with only a single commercial quad operational amplifier (OA) integrated circuit. Methods: A novel compensation strategy was used to provide a transfer function with only one zero at the origin, which makes it easy to comply with the transient response imposed by biomedical standards. A topology with no grounded components was leveraged to obtain a common-mode rejection ratio (CMRR) ideally infinite and independent of components mismatches. Results: Design equations are presented and, as an example, an electrocardiogram (ECG) amplifier was built and tested. It features a CMRR of 102 dB at 50 Hz, 55 dB gain that supports DC input voltages up to ±300 mV when powered from a 0 V to 5 V single-supply voltage, and a cutoff frequency of less than 0.05 Hz with a first order response. Conclusion: A fully-differential biopotential front-end was designed and validated through experimental tests, demonstrating proper operation with only 4 OAs. Significance: The amplifier is intended for board-level design solutions, it can be built with off-the-shelf components that can be selected according to specific needs, such as reduced power consumption, low noise, or proper operation from a low-voltage power source. | en |
dc.language | en | es |
dc.subject | Biopotential measurement | es |
dc.subject | fully-differential amplifier | es |
dc.subject | low cost design | es |
dc.title | A fully-differential biopotential amplifier with a reduced number of parts | en |
dc.type | Articulo | es |
sedici.identifier.other | https://doi.org/10.1109/TIM.2022.3220284 | es |
sedici.creator.person | Spinelli, Enrique Mario | es |
sedici.creator.person | García, Pablo Andrés | es |
sedici.creator.person | Guerrero, Federico Nicolás | es |
sedici.creator.person | Catacora, Valentín Andrés | es |
sedici.creator.person | Haberman, Marcelo Alejandro | es |
sedici.subject.materias | Ingeniería Electrónica | es |
sedici.description.fulltext | true | es |
mods.originInfo.place | Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales | es |
sedici.subtype | Articulo | es |
sedici.rights.license | Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) | |
sedici.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | |
sedici.description.peerReview | peer-review | es |
sedici.relation.journalTitle | IEEE Transactions on Instrumentation and Measurement | es |
sedici.relation.journalVolumeAndIssue | vol. 71 | es |