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dc.date.accessioned 2023-11-29T13:49:55Z
dc.date.available 2023-11-29T13:49:55Z
dc.date.issued 2023
dc.identifier.uri http://sedici.unlp.edu.ar/handle/10915/160854
dc.description.abstract Systems known as SoC-FPGAs have experienced a growing popularity in recent years. This devices integrate field programmable gate arrays with elements such as microprocessors, PLLs and embedded memory blocks. The advantages of this type of systems are clear: great reconfigurability, performance, and energy efficiency, but they come with an negative side: programming and optimizing the applications that use them remains a long and complicated process. In particular, realtime signal processing at high frequencies is an application that can clearly benefit from the advantages of SoC-FPGAs, but the complex workflow assosiated with them usually prevents the designers from taking advantage of its capabilities. In this work, an open source SoC-FPGA platform, specifically intended for signal processing is presented, with the aim of alleviating this workflow. The platform structure is described, specifying the places where the designer may implement their algorithms, and then its operation is demonstrated by acquiring a signal at a maximum sampling frequency of 65 MHz and passing it through a 32th order FIR filter, verifying that the it meets it’s expected theoretical response. The whole system can operate at a maximum frequency of 85 Mhz, has a latency of 16 clock cycles, and uses less than half of the resources of a Cyclone V device. en
dc.language en es
dc.subject SoC-FPGA es
dc.subject Signal Processing es
dc.subject Open source es
dc.subject Filtering es
dc.title Open-source SoC-FPGA Platform for Signal Processing en
dc.type Objeto de conferencia es
sedici.creator.person Oliva, Matías Javier es
sedici.creator.person García, Pablo Andrés es
sedici.creator.person Spinelli, Enrique Mario es
sedici.creator.person Veiga, Alejandro Luis es
sedici.subject.materias Ingeniería es
sedici.description.fulltext true es
mods.originInfo.place Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales es
sedici.subtype Objeto de conferencia es
sedici.rights.license Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
sedici.rights.uri http://creativecommons.org/licenses/by-nc-nd/4.0/
sedici.date.exposure 2023-03
sedici.relation.event XI Southern Programmable Logic Conference (San Luis, 27 al 31 de marzo de 2023) es
sedici.description.peerReview peer-review es


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Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) Excepto donde se diga explícitamente, este item se publica bajo la siguiente licencia Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)