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dc.date.accessioned 2012-10-16T14:17:14Z
dc.date.available 2012-10-16T14:17:14Z
dc.date.issued 2004
dc.identifier.uri http://sedici.unlp.edu.ar/handle/10915/22492
dc.description.abstract The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost. en
dc.language en es
dc.subject Parallel processing es
dc.subject AES en
dc.subject cipher en
dc.subject Distributed es
dc.subject cryptography en
dc.subject FPGA en
dc.subject VHDL en
dc.title Minimum area, low cost fpga implementation of aes en
dc.type Objeto de conferencia es
sedici.creator.person Liberatori, Mónica Cristina es
sedici.creator.person Bonadero, Juan Carlos es
sedici.description.note Eje: IV - Workshop de procesamiento distribuido y paralelo es
sedici.subject.materias Ciencias Informáticas es
sedici.description.fulltext true es
mods.originInfo.place Red de Universidades con Carreras en Informática (RedUNCI) es
sedici.subtype Objeto de conferencia es
sedici.rights.license Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
sedici.rights.uri http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
sedici.relation.event X Congreso Argentino de Ciencias de la Computación es
sedici.description.peerReview peer-review es


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Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) Excepto donde se diga explícitamente, este item se publica bajo la siguiente licencia Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)