FIPBLOX: a graphical interactive design tool for FIPSOC

Abstract

FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.