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Mostrar registro sencillo 2008-05-20T18:01:42Z 2008-05-20T03:00:00Z 2006-04
dc.description.abstract Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics. en
dc.format.extent p. 1-7 es
dc.language en es
dc.title Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures en
dc.type Articulo es
sedici.identifier.uri es
sedici.identifier.issn 1666-6038 es
sedici.creator.person Villa, Francisco J. es
sedici.creator.person Acacio Sánchez, Manuel es
sedici.creator.person García Carrasco, José Manuel es
sedici.subject.materias Ciencias Informáticas es
sedici.description.fulltext true es Facultad de Informática es
sedici.subtype Articulo es
sedici.rights.license Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)
sedici.description.peerReview peer-review es
sedici2003.identifier ARG-UNLP-ART-0000000549 es
sedici.relation.journalTitle Journal of Computer Science & Technology es
sedici.relation.journalVolumeAndIssue vol. 6, no. 1 es
sedici.subject.acmcss98 Multiple Data Stream Architectures (Multiprocessors) es
sedici.subject.acmcss98 Cache memories es

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Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0) Excepto donde se diga explícitamente, este item se publica bajo la siguiente licencia Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)