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dc.date.accessioned 2011-03-30T19:38:47Z
dc.date.available 2011-03-30T03:00:00Z
dc.date.issued 2011-04
dc.identifier.uri http://sedici.unlp.edu.ar/handle/10915/9690
dc.description.abstract This paper presents a parallel architecture for a radial basis function (RBF) neural network used for pattern recognition. This architecture allows defining sub-networks which can be activated sequentially. It can be used as a fruitful classification mechanism in many application fields. Several implementations of the network on a Xilinx FPGA Virtex 4-(xc4vsx25) are presented, with speed and area evaluation metrics. Some network improvements have been achieved by segmenting the critical path. The results expressed in terms of speed and area are satisfactory and have been applied to pattern recognition problems. en
dc.format.extent 15-20 es
dc.language en es
dc.subject PATTERN RECOGNITION es
dc.subject Redes Neurales (Computación) es
dc.subject Parallel Architectures es
dc.title Hardware radial basis function neural network automatic generation en
dc.type Articulo es
sedici.identifier.uri http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr11-3.pdf es
sedici.identifier.issn 1666-6038 es
sedici.creator.person Leiva, Lucas es
sedici.creator.person Acosta, Nelson es
sedici.subject.materias Ciencias Informáticas es
sedici.description.fulltext true es
mods.originInfo.place Facultad de Informática es
sedici.subtype Articulo es
sedici.rights.license Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)
sedici.rights.uri http://creativecommons.org/licenses/by-nc/3.0/
sedici.description.peerReview peer-review es
sedici2003.identifier ARG-UNLP-ART-0000007128 es
sedici.relation.journalTitle Journal of Computer Science & Technology es
sedici.relation.journalVolumeAndIssue vol. 11, no. 1 es


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Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0) Excepto donde se diga explícitamente, este item se publica bajo la siguiente licencia Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)