Metrics for fast, low-cost adders in FPGA

Abstract

In this paper several adder design techniques that probed to be very effective in full-custom integrated circuit design are presented as well as the conclusions regarding its implementation on FPGA. Particularly, in this work, Xilinx XC4000E family is selected as target technology and results achieved without using dedicated carry logic present in these devices are evaluated. This paper aims to substantiate the fact that these techniques indeed reduce delay time in other technologies than full custom design and from these results decide if it is worth trying implementations using XC4000E dedicated carry logic.